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quartusII simulation ok but pins stuck at vcc of gnd

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Hi. Thanks to all of you out there who are helping to solve problems. Now here's one that I need help with....

I've created a component in VHDL which simulates and works properly when used in Altera-Modelsim with a testbench file.

The component I have created also calls up a sub-component, a dual-port RAM created by Mega-wizard pulg-in.

When I try to compile my top-level design (which calls up my user component, which in turn calls up the dual port RAM) I get the error message 'pins stuck at VCC or GND for all the outputs of the dual port RAM.

In the toplevel design I call up my user component which, for test purposes has all its I/Os mapped straight to device pins (directly or via a STD_LOGIC_VECTOR to/from integer conversion), so that no inputs should be fixed at vcc or gnd.

Therefore no outputs should be fixed at vcc or gnd.
So why does my design simulate perfectly okay and yet give these warnings when compiled on quartusII?

Some of the outputs from my component are actually changing and not stuck at vcc or gnd, but all of the q outputs from the dual port ram are stuck at vcc or gnd

Any ideas??? thanks!!

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